Semiconductor integrated circuit (IC) fabrication involves forming layers of patterns on a semiconductor wafer. Each layer has to be aligned with previous layer(s) such that the IC can function properly. Various marks, such as alignment marks and overlay marks, can be used for aligning the layers. In addition, overlay marks are also used for monitoring overlay deviation between layers. Overlay deviation includes misalignment in the position, size, and shape between overlay marks at successive layers. Overlay mark misalignment may be caused by various factors such as aberration and focus position of the projection optical system when transferring patterns from a photomask to a wafer. In addition, fabrication processes such as etching and chemical mechanical polishing (CMP) are likely to affect overlay mark alignment as well.
As semiconductor technology continues progressing to smaller and smaller feature sizes, alignment requirements become more and more stringent. Accordingly, it is desirable to reduce or minimize overlay deviations.